Question

Is Verilog better than VHDL?

Answer 1

VHDL is more verbose than Verilog and it is also has a non-C like syntax. With VHDL, you have a higher chance of writing more lines of code. ... Verilog has a better grasp on hardware modeling, but has a lower level of programming constructs. Verilog is not as verbose as VHDL so that's why it's more compact.Apr 11, 2016